1. Field of the Invention.
This invention relates to memory systems and, in particular, to a No-Fall-Through, First-In-First-Out memory device having high-speed throughout and which is protected against erroneous states and loss of data.
2. Discussion of the Prior Art.
First-In-First-Out (FIFO) memories are a special class of digital electronic read/write memory in which data words are written and read in sequential manner. Because their write and read operations may occur at different rates, FIFO memories find particular application as buffers between systems. Data words written into a FIFO device are later read once from a separate data bus, using a separate clock, in the same sequence a previously written.
A FIFO is said to be "empty" when any data words which have been written into the device have also been read; a FIFO is said to be "full" when the number of data words written into the device exceeds the number of data words which have been read by the "depth" of the device.
FIFO memories are typically cascadable. That is, multiple FIFO devices can be interconnected in series to operate as a FIFO memory system several times deeper than an individual FIFO device; similarly, multiple FIFO devices can be interconnected in parallel to operate as a FIFO memory system several times wider than an individual device.
A bipolar FIFO memory is disclosed in U.S. Pat. No. 4,151,609, issued Apr. 24, 1979, to Moss. The FIFO memory disclosed therein comprises a memory register which stores data words, an input control section, a register control section, and an output control section. The input control section allows data to be written into the FIFO register. The register control section shifts the data hhrough the register, with data queuing up sequentially at the register locations closest to the register output. The output control section allows data to be read from the FIFO register at a rate different than the rate at which data is written into the register by the input control section. In addition to shifting data through the register, the register control section also monitors both the succeeding location and the previous location of data words in the register to determine when data may be shifted.
Use of the Moss FIFO device is limited by the fact that it is a "fall-through" device. A substantial period of time is required to cycle a data word through the register from its first input block to the output block. That is, a number of cycle times equal to the depth of the register are required to allow a data word to "fall through" the Moss FIFO register from the first input block so that it is available for output.
FIFO memory devices are available which are of the "no-fall-through" type. In a "no-fall-through" FIFO memory, newly input data words become quickly available for output.
A No-Fall-Through FIFO memory is described in a United Technologies Mostek Preliminary Data Sheet, "512.times.9 BiPORT.TM.PARALLEL IN-OUT FIFO MK4501 N-12, 15, 20" February 1983. The MK4501 utilizes a two port memory cell, asynchronous read/write operations, and full and empty status flags. The full and empty flags are used to prevent data underflow and overflow. The time required for retrieval of newly input data is about one write cycle. Because write and read operations are internally sequential, no address information is required.
The Mostek device is a relatively slow device, operating at about 7-15 MHz at 4.5-5.5 volts. It also requires additional pins for operation in the cascaded mode. Its read and write cycles must be in a proper state before the device may be reset. Therefore, it is limited in its application.